搜索资源列表
serial2parallel
- 自己用的simulink串并,并串转换子系统-serial to parallel
par2ser
- 并/串转换器即并行输入、串行输出转换器,例如一个8bit输入的并/串转换器,输出时钟频率是输入时钟频率的8倍,输入端一个时钟到来,8个输入端口同时输入数据;输出端以8倍的速度将并行输入的8bit串行输出,至于从高位输出还是从低位输出,可以再程序中指定。-And/or parallel series converter input, serial output converter, for example, a 8bit input and/series converter, the output
rs232
- 串口232程序,实现并串转换及相应的操作-Serial 232 program, to achieve and string conversion and the corresponding operation
shift8
- 用VHDL语言在QUARTUS环境下开发,功能是并串转换移位寄存器-Using VHDL language QUARTUS development environment, and the string conversion function is the shift register
5b6b
- 5B6B码是光纤数字通信系统中使用比较广泛的一种线路码型! 数据经过5B6B编码和并串转换后在光纤上传输,串行码序列中连续的比特0或比特1的长度不超过5,数据在0和1之间变换的密度很高,并具有直流平衡的特性,有利于接收电路和时钟恢复电路的设计。-5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conver
c_bchange
- 实现数据的串行转并行运算,并连续转换,每转换16个数据后,发出一个使能信号-Serial transfer of data parallel computing, and continuous change, each of 16 data conversion, issue an enable signal
SHFRT1_4
- 4位并入串出移位寄存器,实现并串转换,简单易行,通过时序验证.-4-bit shift register into the string out to achieve and string conversion, simple, through sequence verification.
OFDM
- OFDM下行的仿真1、产生要传输随机数; 2、进行调制; 3、串并转换; 4、进行IFFT操作(代码中有用到共轭对称向量的IFFT为实数进行简化计算); 5、增加循环前缀; 6、并串转换; 7、输出前滤波; 8、增加信道噪声(加性高斯白噪声); 9、接收端串并转换; 10、去除循环前缀; 11、进行FFT变换; 12、信号解调; 13、误比特率计算; -OFDM downlink simulation 1, have t
uartin
- 串口通信,实现数据的串并转换,以及并串转换-Serial communication, serial and parallel data conversion, and parallel to serial conversion
OFDM
- 基于对比BPSK系统的OFDM仿真结果分析,把N个子载波上的传输符号通过IFFT,然后并串转换后传输,在接收端通过串并转换后再进行FFT变换-BPSK OFDM system based on comparative analysis of simulation results, the N sub-carrier transmission symbols by IFFT, and the string conversion and transmission, the receiver stri
ser_para
- 用verilog语言来实现并串转换模块,并行输入八个10位,串行输出一个10位。-achieve and serial converter module verilog
p-to-s
- 采用VHDL语言编制的并串转换程序,大家看看吧-Prepared using VHDL language and string conversion process, we look at it
parallel-to-serial-conversion
- 该模块实现的是并串转换功能,经过仿真验证没有问题-This module is designed to implement parallel to serial conversion
zhuan
- 一个关于串并和并串转换的verilog的工程,代码简洁易懂-this is a sample program project for transformation
hc595
- HC595并串转换程序,Verilog语言编写,经过硬件平台测试-HC595 and string conversion process, Verilog language, after testing the hardware platform
123
- 4位并串转换器,VHDL实现。希望给大家提供参考和帮助,其中可能存在商榷位置处。-It is good sample,hope help others.
bis
- 这是个并串转换的程序,用vhdl编写,希望对大家有用。-This is a string and the conversion process, using vhdl write, want to be useful.
p2s
- verilog语言实现的并串转换,适用于quartus环境-the verilog language and string conversion for quartus environment
ADzhuanhuanmokuaisheji
- ad转换模块设计,在模数转换中重要作用,由FPGA控制,分频、串并及并串转换等-ad conversion module design, analog to digital conversion in an important role in
conver
- 非常详细,通俗易懂的并串转换电路得设计,为大家提供思路-very in detail,understandable circuit source